• DocumentCode
    2405902
  • Title

    Minimizing energy consumption for high-performance processing

  • Author

    Weglarz, Eric F. ; Saluja, Kewal K. ; Lipasti, Mikko H.

  • Author_Institution
    Wisconsin Univ., Madison, WI, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    199
  • Lastpage
    204
  • Abstract
    Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowered voltage and frequency to perform a similar amount of work in less time and lower power than a uniprocessor The paper also studies the effect of reducing cache and Branch Target Buffer (BTB) sizes for further reducing power consumption while still providing adequate performance. The best configuration requiring four processors reduced energy by 56%. Reducing cache and BTB provided a further 16% savings in energy while still finishing the workload in the same amount of time as the uniprocessor
  • Keywords
    cache storage; computer architecture; computer power supplies; minimisation; multiprocessing systems; power consumption; Branch Target Buffer; cache size reduction; configuration; design of microprocessors; high-performance processing; multiple constrained processors; power consumption; speed reduction; voltage reduction; Batteries; Circuits; Clocks; Delay; Energy consumption; Finishing; Frequency; Microprocessors; Surface-mount technology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
  • Conference_Location
    Bangalore
  • Print_ISBN
    0-7695-1441-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2002.994919
  • Filename
    994919