Title :
Implant dose sensitivity of 0.1 μm CMOS inverter delay
Author :
Srinivasaiah, H.C. ; Bhat, Navakanta
Author_Institution :
ECE Dept., Indian Inst. of Sci., Bangalore, India
Abstract :
The simulation experiment is performed to characterize the impact of process level fluctuations on the circuit performance variation for the 0.1 μm CMOS technology. The 0.1 μm NMOS and PMOS transistors are optimized using four different ion implantation steps namely super steep retrograde channel (SSRC) implant, deep s/d implant, shallow s/d extension implant and halo implant. We demonstrate that the fluctuations in the nominal values of these implant doses result in the significant variation in DC (Ioff, Ion, Vt) and AC (Cgg) parameters of the transistors. The DC and AC parameter variations of these devices in turn have their effect on the performance of the inverter circuit. In particular, the halo implant has the maximum impact resulting in ΔIoff=122% (97.48%) and ΔI on=4.82% (5.29%) for NMOS (PMOS) transistor. The worst case delay variation is more than ±10% for a ±10% random variation in the implant dose parameters
Keywords :
CMOS integrated circuits; MOSFET; circuit optimisation; delays; integrated circuit modelling; ion implantation; logic gates; 0.1 μm CMOS technology; 0.1 micron; AC parameter variations; DC parameter variations; NMOS transistors; PMOS transistors; circuit performance variation; deep implant; fluctuations; halo implant; ion implantation; process level fluctuations; random variation; shallow extension implant; super steep retrograde channel implant; worst case delay variation; CMOS process; CMOS technology; Circuit optimization; Circuit simulation; Delay; Fluctuations; Implants; Inverters; MOS devices; MOSFETs;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994925
