Title :
History effect characterization in PD-SOI CMOS gates
Author :
Casu, M.R. ; Flatresse, P.
Author_Institution :
Politecnico di Torino, Italy
Abstract :
Partially depleted SOI CMOS gates with floating body exhibit variable propagation delays because of the history effect. In this paper we address the problem of how to find the steady-state in a CMOS gate without resorting to huge computer resources. Moreover, a simple method for the evaluation of delay upper and lower bounds is described.
Keywords :
CMOS integrated circuits; elemental semiconductors; integrated circuit modelling; silicon; silicon-on-insulator; PD-SOI CMOS gates; Si-SiO2; floating body; history effect; lower bounds; partially depleted SOI CMOS gate; steady-state; upper bounds; variable propagation delays; CMOS integrated circuits; Integrated circuit modeling; Silicon; Silicon on insulator technology;
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
DOI :
10.1109/SOI.2002.1044417
