Title :
Application of 3D CMOS technology to SRAMs
Author :
Liu, Christianto C. ; Tiwari, Sandip
Author_Institution :
Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
Abstract :
Through large reductions in area and compatibility with logic, 3D CMOS provides a fruitful path for stand-alone SRAMs and high-performance logic designs. Important factors - cell area, static noise margin, access time, and leakage current are addressed in this paper for 3D SRAM implementations.
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit noise; leakage currents; logic circuits; silicon-on-insulator; 3D CMOS technology; SRAM; access time; cell area; high-performance logic designs; leakage current; static noise margin; CMOS integrated circuits; Integrated circuit noise; Leakage currents; Logic circuits; SRAM chips; Silicon on insulator technology;
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
DOI :
10.1109/SOI.2002.1044421
