2nd- and 4th-order ΣΔ modulators fabricated in 3.3 V 0.5 μm SOS-CMOS for high-temperature applications

Author

Ericson, M.N. ; Rochelle, J.M. ; Bobrek, M. ; Britton, C.L. ; Bobrek, A. ; Blalock, B.J. ; Schultz, R. ; Moore, J.A.

Author_Institution

Oak Ridge Nat. Lab., TN, USA

fYear

2002

fDate

7-10 Oct 2002

Firstpage

75

Lastpage

77

Abstract

A ΣΔ modulator fabricated in 0.5μm SOS-CMOS is reported. The design incorporates two 2nd-order loops allowing reconfigurability as either a 2nd-order single loop or a 4th-order 2-2 cascade. Test results of both modulator configurations over a temperature range of 25°C-200°C are presented. The modulator achieves an effective resolution of 15.5 bits at 25°C and 13.5 bits at 200°C (both at 2KS/s). Design details pertaining to topological selection and device sizing is presented with an emphasis on temperature tolerance. Results of modulator noise analysis is presented along with techniques for improving the modulator noise performance. This paper reports the first 4th-order ΣΔ modulator fabricated in an SOI/SOS process.

Keywords

CMOS integrated circuits; high-temperature electronics; integrated circuit noise; sigma-delta modulation; silicon-on-insulator; ΣΔ modulators; 0.5 micron; 25 to 200 degC; 3.3 V; SOI/SOS process; SOS-CMOS; Si; device sizing; high-temperature applications; modulator configurations; modulator noise analysis; modulator noise performance; reconfigurability; resolution; temperature tolerance; topological selection; CMOS integrated circuits; Integrated circuit noise; Sigma-delta modulation; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, IEEE International 2002

Print_ISBN

0-7803-7439-8

Type

conf

DOI

10.1109/SOI.2002.1044424

Filename

1044424