Transistor flaring in deep submicron-design considerations

Author

Singhal, Vipul ; Keshav, C.B. ; Sumanth, K.G. ; Suresh, P.R.

fYear

2002

fDate

2002

Firstpage

299

Lastpage

304

Abstract

The deep sub-micron regime has brought-up several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors, which causes the channel length to vary along the transistor width. This seriously impacts CMOS process self-alignment, causes transistor-matching issues, and makes accurate transistor modeling difficult. It can have significant adverse yield impact. In this paper, the effect, its consequences, and different solutions are examined. A methodology for modeling the effect of flaring on transistor performance is introduced. Different solutions for high density and high performance designs are proposed

Keywords

CMOS integrated circuits; MOSFET; SPICE; design for manufacture; integrated circuit design; integrated circuit modelling; integrated circuit yield; photolithography; proximity effect (lithography); CMOS process self-alignment; CMOS yield; SPICE models; channel length; circuit design; circuit performance; design considerations; design for manufacturability; high density designs; high performance designs; manufacturing issues; optical proximity correction; photolithography; transistor flaring; transistor modeling; transistor performance; transistor width; transistor-matching; CMOS process; Circuits; Costs; Geometrical optics; Lithography; Manufacturing processes; Semiconductor device modeling; Silicon; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.

Conference_Location

Bangalore

Print_ISBN

0-7695-1441-3

Type

conf

DOI

10.1109/ASPDAC.2002.994938

Filename

994938