Title :
A logic-process-compatible SOI DRAM gain cell operating at 0.5 volt
Author :
Terauchi, Mamoru
Author_Institution :
Dept. of Comput. Eng., Hiroshima City Univ., Japan
Abstract :
A novel SOI DRAM gain cell operating at 0.5 V is proposed. It consists of a p-channel JFET and an n-channel MOSFET, whose source diffusion functions as gate diffusion of the JFET as well. Signal charge is stored in the gate diffusion capacitance of the JFET, leading to the modulation in its source-drain conductance. Mixed-mode simulation with the use of a device simulator reveals that the proposed SOI DRAM gain cell is able to operate properly under supply voltage as low as 0.5 V.
Keywords :
DRAM chips; MOSFET; SPICE; digital simulation; junction gate field effect transistors; semiconductor device models; silicon-on-insulator; 0.5 V; JFET gate diffusion; MOSFET source diffusion; MOSFET switch; Medici device simulator; gate diffusion capacitance; logic-process-compatible SOI DRAM gain cell; low supply voltage; mixed-mode simulation; n-channel MOSFET; p-channel JFET; signal charge storage; simulated cut-off characteristics; source-drain conductance modulation; uniform impurity profile; DRAM chips; JFETs; MOSFETs; SPICE; Semiconductor device modeling; Silicon on insulator technology;
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
DOI :
10.1109/SOI.2002.1044428
