Title :
Fringing-induced barrier lowering (FIBL) effects of 100 nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer
Author :
Lin, S.C. ; Kuo, J.B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
This paper reports the fringing-induced barrier lowering (FIBL) effects of 100 nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer structure. Based on the study, with a higher k gate dielectric, the subthreshold slope is less steep due to the reduced potential barrier in the surface channel caused by a larger vertical electric field in the LDD region under the sidewall oxide spacer next to the drain.
Keywords :
MIS devices; MOS integrated circuits; silicon-on-insulator; 100 nm; FD SOI NMOS devices; LDD/sidewall oxide spacer structure; VLSI; fringing-induced barrier lowering; high permittivity gate dielectrics; reduced potential barrier; subthreshold slope; surface channel; vertical electric field; MIS devices; MOS integrated circuits; Silicon on insulator technology;
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
DOI :
10.1109/SOI.2002.1044431
