Title :
A 60 mW per lane, 4 × 23-Gb/s 27 PRBS generator
Author :
Laskin, E. ; Voinigescu, S.P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fDate :
30 Oct.-2 Nov. 2005
Abstract :
An ultra-low-power, 4-channel 227 - 1 PRBS generator with 60 mW per channel was designed, fabricated and measured to work up to 23 Gb/s. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10-Gb/s. The chip also includes an integrated PRBS checker and error counter.
Keywords :
BiCMOS logic circuits; low-power electronics; random sequences; 2.5 mW; 60 mW; BiCMOS CML latch topology; BiCMOS cascode; error counter; integrated PRBS checker; pseudorandom bit sequence generator; Automatic testing; BiCMOS integrated circuits; Circuit testing; Clocks; Counting circuits; Delay; Energy consumption; Power generation; Signal generators; Switches;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. IEEE
Print_ISBN :
0-7803-9250-7
DOI :
10.1109/CSICS.2005.1531808
