Carrier recombination and thin gate oxide effects in floating body SOI MOSFETs: influence of the device geometries and architectures

To face the SIA roadmap constraints, the natural benefits of the SOI devices should be combined with aggressive scaling. The main ingredients for optimizing the SOI-MOSFETs architecture are film and gate oxide thickness, doping profiles (channel, halos and LDD regions) and lateral isolation techniques. In this paper, we show that the characteristics of floating body SOI devices are modified at low drain voltage by a gate to body current when the gate oxide thickness is as low as 2 nm. Carrier recombination and transconductance measurements versus gate voltage show that the modifications depend both on the geometries and device architecture (doping profiles).