• DocumentCode
    2406486
  • Title

    Low-temperature oxide-bonded three-dimensional integrated circuits

  • Author

    Warner, K. ; Burns, J. ; Keast, C. ; Kunz, R. ; Lennon, D. ; Loomis, A. ; Mowers, W. ; Yost, D.

  • Author_Institution
    Lincoln Lab., MIT, Lexington, MA, USA
  • fYear
    2002
  • fDate
    7-10 Oct 2002
  • Firstpage
    123
  • Lastpage
    124
  • Abstract
    A low-temperature oxide-oxide bond process has been proposed that permits stacking and interconnecting circuit layers with tungsten plugs with size and pitch approaching current 2D-via designs. The oxide bond process is also compatible with the 400-500 °C anneals used to improve transistor properties that complete wafer fabrication. In this paper, the authors report the development of this process, including operational circuits and 3-tier via chains fabricated using concentric vias.
  • Keywords
    CMOS integrated circuits; annealing; chemical mechanical polishing; integrated circuit manufacture; silicon-on-insulator; surface energy; voids (solid); wafer bonding; 2-tier SOI CMOS circuits; 3-tier concentric via chains; 3D circuit fabrication; 400 to 500 degC; SiO2; annealing compatibility; chemical-mechanical polishing; low-temperature oxide-oxide bond process; operational circuits; operational ring oscillators; wafer bonding; Annealing; CMOS integrated circuits; Integrated circuit manufacture; Silicon on insulator technology; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, IEEE International 2002
  • Print_ISBN
    0-7803-7439-8
  • Type

    conf

  • DOI
    10.1109/SOI.2002.1044445
  • Filename
    1044445
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2406486