Bipolar leakage modeling for switch-level simulators

Bipolar leakage is problematic; it can cause noise upset in dynamic circuits and can increase SRAM access time. Accurate (transient) simulation of charge loss due to bipolar leakage requires modeling the SOI-MOSFET as a network of diodes and capacitors, and then solving for the body voltage and bipolar leakage current. Such complexity is incompatible with the operation of approximate simulators (e.g., switch-level), which provide fairly accurate and very fast simulations relative to SPICE. A preliminary model for approximate simulators has been developed; it targeted the case of bipolar leakage triggered by full logic swing signals. In this paper, a more accurate bipolar leakage model which handles arbitrary signals, including noise pulses, is presented.