VLSI architecture for a flexible motion estimation with parameters

If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can obtain benefits, which improve quality and performance, reduce power consumption and optimize the system. In this paper we propose a reconfigurable approach to the motion estimation algorithm and architecture. The proposed algorithm determines motion type and then selects an adapted algorithm in order to improve the quality and performance of images. We implemented the flexible and reconfigurable architecture by hardware with an address generator unit, delay unit, and parameters. Our architecture supports more than one block-matching algorithm and parameters providing an optimized system. We are implementing our architecture by using hardware description language (VHDL) and synthesis design tools. We analyze the performance of architecture and present adaption to the algorithm for a low cost real time application