Up to 80-Gbit/s operations of 1:4 demultiplexer IC with InP HBTs

Author

Sano, Kimikazu ; Fukuyama, Hiroyuki ; Murata, Koichi ; Kurishima, Kenji ; Kashio, Norihide ; Enoki, Takatomo ; Sugahara, Hirohiko

Author_Institution

NTT Photonics Labs., NTT Corp., Kanagawa, Japan

fYear

2005

fDate

30 Oct.-2 Nov. 2005

Abstract

We report up to 80-Gbit/s operations of a 1:4 demultiplexer (DMX) IC with InP HBTs of f_T=292 GHz, f_max=308 GHz. The circuit features are 1) the multiphase clock (MPC) architecture to suppress the increase of the power consumption, and 2) the high collector current density of 5.0 mA/μm² for the fastest circuit blocks. To measure the IC at over 50 Gbit/s where available data pulse pattern generators (PPGs) are few, we constructed two-types of data PPGs, which were a purely electrical PPG (E-PPG) and an optoelectronic PPG (OE-PPG). With these technologies, we successfully confirmed the operations up to 80 Gbit/s for the 1:4 DMX IC.

Keywords

bipolar analogue integrated circuits; clocks; demultiplexing equipment; integrated optoelectronics; pulse generators; 292 GHz; 308 GHz; InP; demultiplexer integrated circuits; electrical pulse pattern generator; heterojunction bipolar transistors; high collector current density; multiphase clocks; optoelectronic pulse pattern generator; pulse pattern generators; Bandwidth; Bit error rate; Clocks; Current density; Energy consumption; Heterojunction bipolar transistors; High speed integrated circuits; Indium phosphide; Latches; Photonic integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. IEEE

Print_ISBN

0-7803-9250-7

Type

conf

DOI

10.1109/CSICS.2005.1531834

Filename

1531834