DocumentCode :
2406937
Title :
A new divide and conquer method for achieving high speed division in hardware
Author :
Mohan, K. N Murali ; Rohini, K. ; Kumar, Anshul ; Balakrishnan, M.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
fYear :
2002
fDate :
2002
Firstpage :
535
Lastpage :
540
Abstract :
Presents a new method of performing division in hardware and explores different ways of implementing it. This method involves computing a preliminary estimate of the quotient by splitting the dividend, performing division of each of the parts in parallel and merging them. The estimate is refined iteratively to get the final quotient. This method is significantly fast since it carries out parallel operations to compute the preliminary quotient and makes use of a fast multiplier to refine the result. It is possible to pipeline the execution of the unit yielding further increase in throughput. Speed estimates show that this method yields a much higher throughput than other fast methods, while area and latency are comparable.
Keywords :
digital arithmetic; divide and conquer methods; dividing circuits; multiplying circuits; parallel processing; area; divide and conquer method; fast multiplier; final quotient; high speed division; latency; parallel operations; throughput; Computer science; Concurrent computing; Delay; Hardware; Iterative algorithms; Merging; Parallel processing; Pipelines; Throughput; Yield estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Print_ISBN :
0-7695-1441-3
Type :
conf
DOI :
10.1109/ASPDAC.2002.994974
Filename :
994974
Link To Document :
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