Title :
An upper bound for 3D slicing floorplans
Author :
Salewski, Silke ; Barke, Erich
Author_Institution :
Inst. of Microelectron. Circuits & Syst., Hannover Univ., Germany
Abstract :
As the impact of interconnect on IC performance and chip area in deep submicron design increases, research activities on technologies for three-dimensional integrated circuits intensify. Nevertheless, there has not been much work done on the automation of 3D-layout design. In this paper we survey slicing structures for 3D floorplans. We present an upper bound for the volume of such floorplans, which shows the usability of slicing structures for three-dimensional floorplanning
Keywords :
VLSI; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; 3D slicing floorplans; IC design; IC interconnect; deep submicron design; slicing structures; three-dimensional integrated circuits; upper bound; Circuits and systems; Design automation; Integrated circuit interconnections; Integrated circuit technology; Microelectronics; Shape; Silicon; Three-dimensional integrated circuits; Upper bound; Usability;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994982
