Title :
A Double Capacitive Body Biased Circuit for High Performance Domino Logic with CMOS Keeper
Author :
Tung, H.-T. ; Thang, N.V. ; Khanh, P.X. ; Kim, S.W.
Author_Institution :
Sch. of Electr., Korea Univ., Seoul, South Korea
Abstract :
In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor is adapted to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard domino (SD) without body bias, dynamic body biased keeper (DBBK) and single capacitive body biased keeper (SCBBK). All the various body biased circuits are applied to a wide fan in OR domino gate for evaluating delay time, power consumption, power-delay product (PDF) and noise immunity. The simulation results with 0.18 mum Hynix CMOS technology show that DCBBK reduces 44%, 22%, 9% in power compare to SD, DBBK, SCBBK while DBBK, SCBBK, DCBBK all improve 46% in speed than SD gate.
Keywords :
CMOS logic circuits; logic gates; 0.18 micron; CMOS keeper; Hynix CMOS technology; OR domino gate; delay time; double capacitive body biased circuit; double capacitive body biased keeper; dynamic body biased keeper; noise immunity; power consumption; power-delay product; single capacitive body biased keeper; standard domino logic; CMOS logic circuits; CMOS technology; Clocks; Delay; Design engineering; Energy consumption; Immune system; Industrial electronics; Logic design; Threshold voltage; Standard domino(SD) logic; double capacitive body bias keeper (DCBBK); dynamic body bias keeper(DBBK); single capacitive body bias keeper(SCBBK);
Conference_Titel :
Communications and Electronics, 2006. ICCE '06. First International Conference on
Conference_Location :
Hanoi
Print_ISBN :
1-4244-0568-8
Electronic_ISBN :
1-4244-0569-6
DOI :
10.1109/CCE.2006.350790
