DocumentCode :
2407254
Title :
The role of subtractive defects and grain boundaries in determining early failures in VLSI metal interconnects
Author :
Poole, K.F. ; Cali, R.R. ; Kemp, K.G.
Author_Institution :
Clemson Univ., SC, USA
fYear :
1991
fDate :
10-12 Mar 1991
Firstpage :
96
Lastpage :
100
Abstract :
Subtractive metal defects which remove more than 50% of the conductor width have an impact on early failures when the grain size is small compared to the feature size. The results of over 300 samples show that for 3 micron wide Al-1%Si conductors with a mean grain size of 0.7 micron, the first failures occur within 10 minutes whilst in the nondefected after 6 hrs. The log normal standard deviation (σ) of the lifetime distribution for the defected stripes is also very large. Defects which remove up to 80% of the metal line width have no effect on early failures in conductors with a grain size of 1.0 micron. These samples exhibit a bamboo structure at the site of the defect. All tests were conducted at 200°C and 1.5×106 Amp/cm2
Keywords :
VLSI; circuit reliability; metallisation; Al-Si alloy; AlSi; VLSI; circuit reliability; grain boundaries; log normal standard deviation; metal defects; metal interconnects failures; subtractive defects; Circuit testing; Conducting materials; Conductors; Current density; Grain boundaries; Grain size; Integrated circuit interconnections; Integrated circuit reliability; Stress; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, 1991. Proceedings., Twenty-Third Southeastern Symposium on
Conference_Location :
Columbia, SC
ISSN :
0094-2898
Print_ISBN :
0-8186-2190-7
Type :
conf
DOI :
10.1109/SSST.1991.138522
Filename :
138522
Link To Document :
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