DocumentCode
2407300
Title
A VLSI array for ensemble operations
Author
Lin, Wen-Tai ; Chin, Chi-Yuan
Author_Institution
Gen. Electr. Co., Schenectady, NY, USA
fYear
1989
fDate
3-5 Jan 1989
Firstpage
101
Lastpage
110
Abstract
Embedding simple switches in a regular VLSI array has been a mainstream effort in the wafer-scale integration fault-tolerant system design. With only a little additional circuitry, these switches can be upgraded into a shuffle bus which provides not only direct data routings but also global communications. Based on the same shuffle-bus architecture, three reconfiguration schemes can be derived. With such flexibility, one can devise a combinational scheme to cope more dynamically with the various static and transient errors. Fundamental bus operations, such as shuffle interconnections on two-dimensional shuffle buses, are systematically derived. This modular array architecture, being suitable for vector and systolic-type processings, can be viewed as an ensemble operator and programmed like a conventional two-operand operator
Keywords
VLSI; cellular arrays; combinatorial circuits; microprocessor chips; VLSI array; combinational scheme; direct data routings; ensemble operations; global communications; modular array architecture; reconfiguration schemes; shuffle bus; systolic-type processings; transient errors; two-operand operator; wafer-scale integration fault-tolerant system design; Circuit faults; Communication switching; Communication system control; Fault detection; Global communication; Integrated circuit interconnections; Routing; Switches; Switching circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9901-9
Type
conf
DOI
10.1109/WAFER.1989.47541
Filename
47541
Link To Document