A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

Author

Domínguez-Castro, R. ; Espejo, S. ; Rodríguez-Vázquez, A. ; Carmona, R.

Author_Institution

Inst. de Microelectron., Seville Univ., Spain

fYear

1997

fDate

12-13 Sep 1997

Firstpage

117

Lastpage

122

Abstract

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; arrays; integrated circuit design; neural chips; parallel processing; CMOS technology; area occupation reduction; electrically-programmable array processors; integration density improvement; linear four-quadrant strategy; local connectivity; massively-parallel analog array processors; one-transistor-synapse strategy; power dissipation reduction; translationally-invariant processing arrays; CMOS process; CMOS technology; Cellular neural networks; Circuits; Computer architecture; Data mining; Motion detection; Paper technology; Power dissipation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Analog and Mixed IC Design, 1997. Proceedings., 1997 2nd IEEE-CAS Region 8 Workshop on

Conference_Location

Baveno

Print_ISBN

0-7803-4240-2

Type

conf

DOI

10.1109/AMICD.1997.637203

Filename

637203