Yield analysis of 2D hexagonal VLSI/WSI arrays

This paper proposes techniques for determining the yield of redundant 2D hexagonal VLSI and WSI arrays. Such arrays are very useful in parallel processing, distributed processing and systolic array applications. Redundancy is implemented at the interstitial spaces of the array structure and reconfiguration is performed locally in order to keep the interconnections short and simple. The first reconfiguration strategy models spare assignment process as discrete parameter Markov-chain with a one-step stochastic transitional probability matrix. The second technique assumes that each hexagonal cell is independent and uses locally interconnected spare processor at interstitial spaces for reconfiguration. The effect on yield and chip-area utilization factor is derived for 50% and 100% redundancy