Parallel compact WY QR factorization for asynchronous message passing

Author

Dunn, Ian N. ; Meyer, Gerard G L

Author_Institution

Wireless Comput. Group, Mercury Comput. Syst. Inc., Chelmsford, MA, USA

fYear

2002

fDate

2002

Firstpage

17

Lastpage

24

Abstract

This paper describes the design, implementation, and performance of a new parallel QR factorization algorithm based on the Compact WY representation of Householder reflections. In contrast to existing parallel algorithms, the multiprocessor partitioning strategy is not governed by an underlying static data distribution scheme. Rather, a dynamic distribution strategy is employed to exploit the capabilities of message passing architectures to overlap computation with communication. Experiments conducted on a 128-processor SGI Origin 2000 and a 64-processor HP SPP-2000 show that this new algorithm has a lower execution time than available tuned parallel routines installed on the machines including a version of ScaLAPACK´s distributed QR factorization algorithm PDGEQRF

Keywords

mathematics computing; message passing; parallel algorithms; Householder reflections; PDGEQRF; QR factorization; ScaLAPACK; WY representation; asynchronous message passing; multiprocessor; parallel algorithm; parallel routines; Algorithm design and analysis; Concurrent computing; Distributed computing; Distribution strategy; Kernel; Message passing; Parallel algorithms; Partitioning algorithms; Process design; Reflection;

fLanguage

English

Publisher

ieee

Conference_Titel

Performance, Computing, and Communications Conference, 2002. 21st IEEE International

Conference_Location

Phoenix, AZ

Print_ISBN

0-7803-7371-5

Type

conf

DOI

10.1109/IPCCC.2002.995132

Filename

995132