Title :
MAX EPLDs offer fast alternatives to ASICs
Author_Institution :
Altera Corp., San Jose, CA, USA
fDate :
Feb. 26 1990-March 2 1990
Abstract :
The complexity and capability of programmable logic devices (PLDs) have increased substantially in the last five years. With this increase, design methodologies, computer-aided-engineering (CAE) tools, and system applications associated with the devices have changed as well. An overview of the evolution of one category of CMOS PLDs, known as erasable programmable logic devices (EPLDs), is provided. Effective logic synthesis requires a set of design tools which accept a designer´s high-level input and implement the required logic functions into these large-scale devices without designer hand-holding, while minimizing implementation cost. When the silicon architecture and design synthesis approaches are developed in parallel, the result is a technology that maximizes designer productivity and minimizes device costs. The logic synthesis issues involved in the efficient use of an innovative PLD architecture as a viable alternative to custom application-specific ICs (ASICs) are discussed.<>
Keywords :
logic CAD; logic arrays; CAE; MAX EPLDs; computer-aided-engineering; design methodologies; design synthesis approaches; erasable programmable logic devices; logic synthesis; programmable logic devices; silicon architecture; Application software; CMOS logic circuits; Computer aided engineering; Cost function; Design methodology; Large-scale systems; Logic design; Logic devices; Logic functions; Programmable logic devices;
Conference_Titel :
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2028-5
DOI :
10.1109/CMPCON.1990.63724
