DocumentCode :
2408793
Title :
Power decoupling with integral capacitors and area array connections
Author :
Diaz-Alvarez, E. ; Krusius, J.P. ; Kroeger, Arid F.
Author_Institution :
Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
fYear :
1998
fDate :
26-28 Oct 1998
Firstpage :
209
Lastpage :
212
Abstract :
Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors in the power distribution network. As operating frequencies increase, the use of decoupling capacitors integrated in the substrate becomes more pressing. We present a partial element equivalent circuit (PEEC) based modeling approach especially suited for such integrated capacitors, together with TDR and high-frequency S-parameter measurement, and model validation via use of specially fabricated test structures
Keywords :
S-parameters; capacitors; equivalent circuits; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; time-domain reflectometry; TDR; area array connections; discrete capacitors; ground decoupling; high-frequency S-parameter measurement; integral capacitors; integrated capacitors; integrated decoupling capacitors; model validation; operating frequency; packaged IC decoupling; partial element equivalent circuit based modeling; power decoupling; power distribution network; test structures; Capacitance; Capacitors; Circuit simulation; Computational complexity; Dielectrics; Electrodes; Maxwell equations; RLC circuits; SPICE; Surface-mount technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on
Conference_Location :
West Point, NY
Print_ISBN :
0-7803-4965-2
Type :
conf
DOI :
10.1109/EPEP.1998.733981
Filename :
733981
Link To Document :
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