Title :
Proceedings Design, Automation and Test in Europe Conference and Exhibition
Abstract :
The following topics are dealt with: ambient intelligence - visions and achievements; energy-efficient memory systems; uncertainty; power-aware design and synthesis; test data compression; operating system abstraction and targeting; embedded software forum; analysis of jitter and noise for analogue systems; semiconductor device modelling and simulation; embedded system scheduling and analysis; DFT and BIST recent advances; analogue and RF modelling, simulation and optimisation; architectural level synthesis; scheduling in reconfigurable computing; delay testing and diagnosis; embedded operating systems for SoC; networks-on-chip; system level modelling; reconfigurable SoC; analogue and defect-oriented testing; energy aware software techniques; interconnect modelling and signal integrity; system level simulation; software optimisation; global approaches to layout synthesis; platform design and IP reuse methods; on-line testing and self-repair; safe automotive software development; mixed-signal design techniques; low power architectures; SoC testing; SAT based verification; highly integrated communication systems; chip estate zoning; asynchronous circuits; collaborative design and WWW-based tools; hardware/software codesign optimization; test pattern generation; low power software; application specific memory synthesis; CAD.
Keywords :
CAD; Internet; asynchronous circuits; automatic test pattern generation; built-in self test; circuit noise; circuit optimisation; circuit simulation; data compression; design for testability; embedded systems; formal verification; groupware; hardware-software codesign; high level synthesis; industrial property; integrated circuit design; integrated circuit testing; intelligent networks; interconnections; jitter; low-power electronics; mixed analogue-digital integrated circuits; operating systems (computers); processor scheduling; reconfigurable architectures; semiconductor device models; semiconductor storage; system-on-chip; telecommunication equipment; uncertain systems; BIST; CAD; DFT; IP reuse; RF modelling; SAT based verification; SoC; WWW-based tools; ambient intelligence; analogue modelling; analogue system noise; application specific memory synthesis; asynchronous circuits; automotive software; chip estate zoning; collaborative design; delay testing; embedded software; energy aware software; energy-efficient memory systems; hardware/software codesign; high level synthesis; integrated communication systems; interconnect modelling; jitter; low power architectures; mixed-signal design; networks-on-chip; on-line testing; operating systems; optimisation; power-aware design; reconfigurable computing; scheduling; self-repair; semiconductor device modelling; signal integrity; simulation; test data compression; test pattern generation; uncertainty; Asynchronous logic circuits; Circuit noise; Circuit optimization; Collaborative work; Communication equipment; Data compression; Design automation; Design for testability; High-level synthesis; Integrated circuit design; Integrated circuit testing; Intelligent networks; Internet; Jitter; Mixed analog-digital integrated circuits; Operating systems; Processor scheduling; Reconfigurable architectures; Self-testing; Semiconductor device modeling; Semiconductor memories; Uncertain systems;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Conference_Location :
Munich, Germany
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253577
