DocumentCode
2408927
Title
A 4 Mbit static RAM
Author
Trilhe, Jacques
Author_Institution
SGS-Thomson Microelectron., Grenoble, France
fYear
1989
fDate
3-5 Jan 1989
Firstpage
193
Lastpage
201
Abstract
The 4.5-Mb static RAM (random access memory) is discussed. After a brief review of the state of the art, the architecture of the static RAM is presented. The technology add-ons are discussed and test strategy and the configuration algorithms are presented
Keywords
VLSI; integrated memory circuits; random-access storage; 4.5 Mbit; architecture; configuration algorithms; static RAM; technology add-ons; test strategy; Collaboration; Image storage; Manufacturing industries; Metals industry; Microelectronics; Random access memory; Read-write memory; Telecommunications; Testing; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9901-9
Type
conf
DOI
10.1109/WAFER.1989.47550
Filename
47550
Link To Document