A case study on different test screening techniques for ICS with high resistance vias interconnects issues

Author

Sim, D. ; Tan, Y.C. ; Low, F. ; Foo, E.G.

Author_Institution

Syst. on Silicon Manuf. Co. Pte. Ltd., Singapore

fYear

2008

fDate

7-11 July 2008

Firstpage

1

Lastpage

5

Abstract

Weak ICs that are functional under normal operating conditions are not easily screened out during CP/FT stages. In this paper, different test screening and reliability assessment techniques were applied on a batch of wafers with normal to highly resistive vias interconnects. The results and effectiveness of these techniques to screen and flag out problematic dies at wafer level testing were presented. . In additional, a fast wafer level interconnect wear-out test (via electromigration test) and a package level burn-in test were also performed to complete the evaluation.

Keywords

integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; wafer level packaging; electromigration test; interconnects issues; normal operating conditions; reliability assessment techniques; test screening techniques; wafer level interconnect wear-out test; wafer level testing; Aluminum; Electromigration; Etching; Manufacturing; Metallization; Packaging; Performance evaluation; Production; Testing; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the

Conference_Location

Singapore

Print_ISBN

978-1-4244-2039-1

Electronic_ISBN

978-1-4244-2040-7

Type

conf

DOI

10.1109/IPFA.2008.4588152

Filename

4588152