A technique for high ratio LZW compression [logic test vector compression]

Author

Knieser, Michael J. ; Wolff, Francis G. ; Papachristou, Chris A. ; Weyer, Daniel J. ; McIntyre, David R.

Author_Institution

Indiana Univ., Indianapolis, IN, USA

fYear

2003

fDate

2003

Firstpage

116

Lastpage

121

Abstract

Reduction of both the test suite size and the download time of test vectors is important in today\´s system-on-a-chip designs. In this paper, a method for compressing the scan test patterns using the LZW algorithm is presented. This method leverages the large number of "don\´t-cares" in test vectors in order to improve the compression ratio significantly. The hardware decompression architecture presented here uses existing on-chip embedded memories. Tests using the ISCAS89 and the ITC99 benchmarks show that this method achieves high compression ratios.

Keywords

boundary scan testing; data compression; logic simulation; logic testing; system-on-chip; LZW algorithm; SoC; compression ratio; download time reduction; hardware decompression architecture; high ratio LZW compression; logic test vector compression; on-chip embedded memories; scan test pattern compression; system-on-a-chip; test suite size reduction; Automatic testing; Benchmark testing; Built-in self-test; Clocks; Computer architecture; Data compression; Hardware; Intellectual property; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253596

Filename

1253596