• DocumentCode
    2409412
  • Title

    Test structure failed node localization and analysis from die backside

  • Author

    Li, Y.G. ; Tan, S.H. ; Sun, W.R.

  • Author_Institution
    Syst. on Silicon Manuf. Co. Pte. Ltd., Singapore
  • fYear
    2008
  • fDate
    7-11 July 2008
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    In this work, backside failure analysis technique on test structure failed node isolation and analysis are presented. Compared to front side failure analysis method, backside failure analysis provides more significant information that is related to the root cause directly. Especially, in the failure situations such as failure related to interface between contact top and metal in the contact chain structure or failure due to high resistance stacked via connected to n+ active P well structure, front side failure analysis isnpsilat effective to localize the failed site or clearly reveal root cause form investigation of defect due to sample preparation shortage. However, backside failure analysis overcomes the limitation of front side analysis. It was applied successfully on open contact chain observation and passive voltage contract (PVC) failed stacked via localization on the n+ active area. Combined with following cross-sectional TEM analysis, the root cause was firmly concluded.
  • Keywords
    CMOS integrated circuits; failure analysis; fault diagnosis; integrated circuit testing; isolation technology; transmission electron microscopy; CMOS integrated circuit; backside failure analysis technique; contact chain structure; cross-sectional TEM analysis; die backside; n+ active P well structure; open contact chain observation; passive voltage contract; root cause analysis; sample preparation shortage; test structure failed node isolation; CMOS integrated circuits; CMOS technology; Contact resistance; Failure analysis; Integrated circuit packaging; Integrated circuit technology; Optical microscopy; Scanning electron microscopy; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-2039-1
  • Electronic_ISBN
    978-1-4244-2040-7
  • Type

    conf

  • DOI
    10.1109/IPFA.2008.4588165
  • Filename
    4588165