DocumentCode
2409711
Title
High-level allocation to minimize internal hardware wastage [high-level synthesis]
Author
Molina, M.C. ; Mendías, J.M. ; Hermida, R.
Author_Institution
Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
fYear
2003
fDate
2003
Firstpage
264
Lastpage
269
Abstract
Conventional synthesis algorithms perform the allocation of heterogeneous specifications, those formed by operations of different types and widths, by binding operations to functional units of their same type and width. Thus, in most of the implementations obtained, some hardware waste appears. This paper proposes an allocation algorithm able to minimize this hardware waste by fragmenting operations into their common operative kernel, which then may be executed over the same functional units. Hence, fragmented operations are executed over sets of several linked hardware resources. The implementations proposed by our algorithm need considerably smaller area than the ones proposed by conventional allocation algorithms. And due to operation fragmentation, in the datapaths produced the type, number, and width of the hardware resources are independent of the type, number, and width of the specification operations and variables.
Keywords
circuit optimisation; high level synthesis; logic design; HLS; common operative kernel; datapaths; fragmented operations; functional unit binding operations; functional unit type; functional unit width; hardware waste; heterogeneous specification allocation; high-level allocation; high-level synthesis; internal hardware wastage minimization; linked hardware resources; operations fragmentation; Circuit synthesis; Europe; Hardware; High level synthesis; Kernel; Logic; Scheduling algorithm; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253618
Filename
1253618
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