DocumentCode
2409891
Title
Non-enumerative path delay fault diagnosis [logic testing]
Author
Padmanaban, Saravanan ; Tragoudas, Spyros
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
2003
fDate
2003
Firstpage
322
Lastpage
327
Abstract
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with a validated non-robust test may together with fault free robustly tested faults be used to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero suppressed binary decision diagram. The proposed method is space and time non-enumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS´85 benchmarks show that the proposed technique is on an average least three times more efficient in improving the diagnostic resolution than existing techniques.
Keywords
binary decision diagrams; combinational circuits; fault diagnosis; logic testing; combinational circuit; diagnostic resolution; digital synchronous circuit; fault free robustly tested faults; nonenumerative path delay fault diagnosis; nonrobust test validation; space nonenumerative method; time nonenumerative method; zero suppressed binary decision diagrams; Boolean functions; Circuit faults; Circuit testing; Data structures; Delay; Fault diagnosis; Integrated circuit testing; Performance evaluation; Robustness; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253627
Filename
1253627
Link To Document