Title :
Simulation of the multi-source/drain SOI MOSFET
Author :
Lin, Po-Hsieh ; Kang, Shiang-Shi ; Lin, Jyi-Tsong ; Eng, Yi-Chuen
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung
Abstract :
In this paper, for the first time, a novel devise-architecture namely multi-source/drain SOI MOSFET is proposed and compared with a conventional SOI MOSFET. According to the simulation result, our proposed transistor not only maintains the desirable short channel behaviour, but also enhances the on/off current ratio due to the multi-source/drain scheme.
Keywords :
MOSFET; electronic engineering computing; semiconductor device reliability; semiconductor process modelling; silicon-on-insulator; DEVISE; multi-source/drain SOI MOSFET; three-dimensional process simulation; Current density; Degradation; Electrons; Etching; FETs; Leakage current; MOS devices; MOSFET circuits; Parasitic capacitance; Silicon on insulator technology;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2039-1
Electronic_ISBN :
978-1-4244-2040-7
DOI :
10.1109/IPFA.2008.4588184
