DocumentCode
2410068
Title
The effect of band gap engineering of the nitride storage node on performance and reliability of charge trap flash
Author
Sandhya, C. ; Ganguly, U. ; Singh, K.K. ; Olsen, C. ; Seutter, S.M. ; Conti, G. ; Ahmed, K. ; Krishna, N. ; Vasi, Juzer ; Mahapatra, S.
Author_Institution
Dept. of EE, IIT Bombay, Mumbai
fYear
2008
fDate
7-11 July 2008
Firstpage
1
Lastpage
7
Abstract
The effect of nitride composition, i.e. Si-rich (Si+) and N-rich (N+) nitride bi-layers separated by an oxynitride (SiON) layer on memory performance and reliability is studied. Bottom Si+ layer and top N+ forms the Si+/N+ bi-layer that is compared to the opposite configuration of N+/Si+ bi-layer to reveal large impact on memory performance and reliability. Si+/N+ bi-layers exhibit superior P/E windows and endurance characteristics but worse retention charge loss compared to N+/Si+ stacks. The oxynitride layer composition and position play a dominant role in trap generation as evident from endurance performance. A low energy-threshold degradation mechanism with higher degradation of the SiON layer with greater H-content is observed. A Si-H bond breaking mechanism is proposed as trap generation mechanism during endurance cycling. Retention is primarily bottom nitride composition dependent as tunnel oxide is shown to be the dominant charge loss path.
Keywords
bonds (chemical); energy gap; flash memories; integrated circuit reliability; interface states; multilayers; nitrogen; silicon; silicon compounds; P/E windows characteristics; Si+-SiON-N+; band gap engineering; bond breaking mechanism; charge loss path; charge trap flash reliability; endurance characteristics; endurance cycling; energy-threshold degradation mechanism; memory performance; nitride bi-layers; nitride composition effect; nitride storage node effects; oxynitride layer composition; retention charge loss; trap generation mechanism; tunnel oxide; Bonding; Capacitors; Degradation; Fabrication; Interference; Material storage; Photonic band gap; Reliability engineering; SONOS devices; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the
Conference_Location
Singapore
Print_ISBN
978-1-4244-2039-1
Electronic_ISBN
978-1-4244-2040-7
Type
conf
DOI
10.1109/IPFA.2008.4588192
Filename
4588192
Link To Document