A rigorous model for trapping and detrapping in thin gate dielectrics

We rigorously model charge trapping and detrapping in ultrathin dielectrics. In addition to charge exchange with the substrate, the poly-gate interface is taken into account which gives rise to decreased charge trapping compared to conventional models designed for thicker gate dielectrics. Finally, an extension of this model also accounting for the shift of trap levels may possibly explain the large time scales experimentally observed during the recovery after application of an on-state voltage.