• DocumentCode
    2410325
  • Title

    A 1000-Gate TTL-Compatible Masterslice Array

  • Author

    Gonauser, E. ; Braeckelmann, W. ; Delker, K. ; Schoen, K.R. ; Wilhelm, W. ; Glasl, A.

  • Author_Institution
    Siemens AG, Munich, Germany
  • fYear
    1980
  • fDate
    22-25 Sept. 1980
  • Firstpage
    76
  • Lastpage
    78
  • Abstract
    A 36.6 mm2 masterslice array with 58 fully TTL-compatible I/O-ports is described. The chip features 1ns internal gate delay, a power dissipation of 0.6 mW per gate and a single 5 V supply.
  • Keywords
    logic gates; transistor-transistor logic; I/O-ports; TTL-compatible masterslice array; internal gate delay; power 0.6 mW; time 1 ns; voltage 5 V; Circuit noise; Delay; Logic; Multiplexing; Power dissipation; Power supplies; Power system economics; Resistors; Switching circuits; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
  • Conference_Location
    Grenoble
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.1980.5468738
  • Filename
    5468738
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2410325