A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design

MPEG Reconfigurable Video Coding project aims at providing more flexible and easier solutions to specify video coders and decoders. Many contributions are devoted to the RVC-CAL language, the standard description language. There are also contributions about the general framework of this new model of video coding, and many CAL descriptions for video algorithms. However, RVC compliant implementations have been only studied next to code generation which does not take advantage of major characteristics of CAL networks as they are dataflow graphs. Consequently, there are no dedicated architectures that are inherently bound to the CAL language. The objective of this article is to present preliminary work about the design of a co-processor based architecture. The co-processor is a reconfigurable architecture that uses CAL network features and proposes a dynamic memory allocation system, which improves the communication between the processes that are implemented, and enables to allocate minimum memory.