DocumentCode :
2410850
Title :
Optimal reconfiguration functions for column or data-bit built-in self-repair
Author :
Nicolaidis, M. ; Achouri, N. ; Boutobza, S.
Author_Institution :
iRoC Technol., Grenoble, France
fYear :
2003
fDate :
2003
Firstpage :
590
Lastpage :
595
Abstract :
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits of the technology, they are more prone to failures than logic. Thus, memories concentrate the large majority of defects and affect circuit yield dramatically. Hence, built-in self-repair is gaining importance. This work presents optimal reconfiguration functions for memory built-in self-repair on the data-bit level. We also present a dynamic repair scheme that allows a reduction of the size of the repairable units. The combination of these schemes allows repairing multiple faults affecting both regular and spare units, by means of low hardware cost. The scheme uses a single test pass, resulting on low test and repair time.
Keywords :
circuit optimisation; integrated circuit testing; integrated memory circuits; logic design; logic testing; maintenance engineering; reconfigurable architectures; system-on-chip; BISR optimal reconfiguration functions; SoC; column BISR; data-bit level built-in self-repair; dynamic repair scheme; embedded memories; memory failures; multiple fault repair; repairable unit size reduction; single test pass; Built-in self-test; Circuit faults; Costs; Fuses; Laser beams; Logic design; Logic devices; Maintenance; Performance evaluation; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN :
1530-1591
Print_ISBN :
0-7695-1870-2
Type :
conf
DOI :
10.1109/DATE.2003.1253672
Filename :
1253672
Link To Document :
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