DocumentCode
2411037
Title
A 16 Bit Self-Testing Multiplier
Author
Rainard, J.-L. ; Vernay, Y.-J.
Author_Institution
Centre de Microelectron. de Grenoble, C.N.E.T., France
fYear
1980
fDate
22-25 Sept. 1980
Firstpage
205
Lastpage
208
Abstract
A single chip integrated multiplier working on 16 bit words dotted with two different operating modes (serial or parallel) and able to signal out any failure by means of an internal supervision system (for some 25% extra silicon area).
Keywords
built-in self test; circuit testing; internal supervision system; self-testing multiplier; single chip integrated multiplier; word length 16 bit; Adders; Built-in self-test; Circuit testing; Clocks; Degradation; Fault tolerant systems; Microprocessors; Registers; Signal processing; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
Conference_Location
Grenoble
Type
conf
DOI
10.1109/ESSCIRC.1980.5468773
Filename
5468773
Link To Document