A 2T Dual Port Capacitor-Less DRAM

A novel two-transistor (2T) dual port capacitor-less DRAM concept based on bulk floating body is demonstrated for the first time in this letter. The read operation can be performed without disturbance of refresh or write. A novel read method is proposed to improve device performance especially at high temperature. Experimental results show a refresh cycle time of 1.28 s, an initial memory window of 192.84 μA/μm, and an initial signal sensing margin of 112.75 μA/μm with ±5 sigma variations at 85°C. The 2T cell is very promising for high-speed, low-power, and low-cost embedded DRAM application.