Empowering ASIC Front-End to Meet the Challenges of the Ultra Deep Sub-Micrometer

The major problem posed by very deep sub-micrometer is the inaccuracies which it introduces into the conventional electronic design automation tool estimates. The estimates of power and speed reported by these tools do not consider the effects posed by very deep sub micrometer because of the non-availability of 45 nm cell libraries. Thus, there is an urgent need of a design flow which results in power and speed predictions at very deep sub micrometer considering the various issues in the same. The objective of this research paper is to analyze the prerequisites for electronic design automation tool which provides the front-end engineer the real insight into the physical manifestation of the design in the deep sub-micron. The tool has been partially implemented using PERL, and has yielded results which have been validated at 180 nm after comparison with conventional synthesis engines. The accuracy of results depends solely on the accuracy of the sub 65 nm models employed for gates and interconnects