High Speed VLSI Design CCMP AES Cipher for WLAN (IEEE 802.11i)

The advanced encryption standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper, we propose a high speed, non-pipelined FPGA implementation of the AES-CCMP (counter-mode/CBC-MAC protocol) cipher for wireless LAN using Xilinx development tools and Virtex-II Pro FPGA circuits. IEEE 802.11i defines the AES-based cipher system, which is operated on CCMP Mode. All the modules in this core are described by using Verilog 2001 language. The developed AES CCMP core is aimed at providing high speed with sufficient security. The encryption/decryption data path operates at 194/148 MHz resulting in a throughput of 2.257 Gbits/sec for the encryption and 1.722 Gbits/sec for decryption. Compared to software implementation, migrating to hardware provides higher level of security and faster encryption speed. A comparison is provided between our design and similar existing implementations