• DocumentCode
    2411721
  • Title

    Power/ground mesh area optimization using multigrid-based technique [IC design]

  • Author

    Wang, Kai ; Marek-Sadowska, Malgorzata

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
  • fYear
    2003
  • fDate
    2003
  • Firstpage
    850
  • Lastpage
    855
  • Abstract
    In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints. The multigrid-based technique is applied to reduce a large-scale mesh to a much coarser one. The reduced mesh can be efficiently optimized. The solution for the original mesh is then computed using a back-mapping process. Experimental results are very encouraging. Large-scale power/ground meshes with millions of nodes can be solved in a few minutes. The proposed technique not only speeds up the optimization process significantly without compromising the quality of solutions, but also brings up the possibility of incorporating the power/ground mesh optimization into other physical design stages such as signal routing.
  • Keywords
    circuit optimisation; integrated circuit design; integrated circuit reliability; logic design; network topology; back-mapping process; coarse mesh; large-scale mesh; mesh topology; multigrid-based technique; optimization speed increase; power/ground mesh area optimization; power/ground network synthesis; reliability constraints; Chip scale packaging; Circuit topology; Constraint optimization; Design optimization; Large-scale systems; Network topology; Routing; Signal design; Signal processing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2003
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1870-2
  • Type

    conf

  • DOI
    10.1109/DATE.2003.1253712
  • Filename
    1253712