Single Bit Read Disturb failure mechanism and transistor size optimization for dual port SRAM bitcell in embedded NVM process SOC applications

We observed Single Bit Read Disturb failure in SRAM blocks with embedded Flash process. Such failures are not observed in pure logic process because pure logic process does not require additional thermal budget. In embedded Flash process, static Noise Margin (SNM) and leakage current degrades, causing more Single Bit Failure (SBF) at high VCC and/or high temperature. We optimized SRAM bitcell´s transistor size and improved the process leakage. We report the procedure for beta optimization and did standby leakage analysis, which points to the location electrically. After the process fix and bitcell beta increase, the SBF problem was resolved and the product became more reliable with more Static Noise Margin (SNM).