Cycling induced degradation of a 65nm FPGA flash memory switch

Author

Schmid, Ben A. ; Jia, James Yingbo ; Wolfman, Jonathan ; Wang, Yu ; Dhaoui, Fethi ; Tseng, Huan-Chung ; Kim, Sung-Rae ; Lee, Kin-Sing ; Liu, Patty ; Han, Kyung Joon ; Hu, Chenming

Author_Institution

Actel Corp., Mountain View, CA, USA

fYear

2010

fDate

17-21 Oct. 2010

Firstpage

92

Lastpage

94

Abstract

We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.

Keywords

field programmable gate arrays; flash memories; integrated circuit interconnections; oxidation; semiconductor switches; FPGA flash memory switch; LDD implant; cell endurance; configurable interconnection switch; cycling induced degradation; embedded-flash process; field programmable gate array; poly re-oxidation; shared floating gate; spacer module; test-array levels; transistor flash memory cell; Degradation; Electron traps; Field programmable gate arrays; Logic gates; Nonvolatile memory; Programming; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International

Conference_Location

Stanford Sierra, CA

ISSN

1930-8841

Print_ISBN

978-1-4244-8521-5

Type

conf

DOI

10.1109/IIRW.2010.5706495

Filename

5706495