DocumentCode
2411996
Title
Downstream electromigration improvement in 45nm technology
Author
Zhao, Yinghong ; Zeng, Xu ; Liu, Wei ; Zhang, Fan ; Lim, Yeow Kheng
Author_Institution
GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, Singapore
fYear
2010
fDate
17-21 Oct. 2010
Firstpage
106
Lastpage
109
Abstract
The broad time-to-failure distribution and bimodality of downstream electromigration (EM) in 45nm technology node are investigated. Liner void and end of line void at wafer edge on downstream EM structure after M1 CMP is a clear physical vapor deposition (PVD) shadowing effect signature caused by poor liner gap fill capability. Furthermore, void growth study during early electromigration stage effectively indicates that the void is initiated at the bottom corner of the via interfacing with cap layer for early failures and slit void is consistently observed at same location on unstressed sample. These pre-existed voids create poor contact either on via bottom interface or trench and cap layer interface or via bottom corner which produce a difference in failure time resulting in poor time to failure (TTF) spread and lower t50. New Cu seed deposition technique eliminates end of line void and liner void and it turns out to improve downstream EM performance. Optimized post etch treatment (PET) chemicals help to reduce Cu oxidation to improve via bottom integrity and eliminate slit void. This effective post etch treatment was demonstrated to improve downstream EM bimodality behavior to tight mono-modal distribution. Via above to metal below overlay is also one of key factors for downstream EM improvement. There is a strong correlation between the TTF and the via to metal overlay and stringent overlay control is beneficial to improve downstream EM sigma and t50.
Keywords
chemical mechanical polishing; copper; electromigration; etching; oxidation; sputter deposition; voids (solid); Cu; cap layer interface; downstream electromigration; end of line void; liner gap fill capability; mono-modal distribution; physical vapor deposition; post etch treatment; seed deposition technique; shadowing effect signature; size 45 nm; time-to-failure distribution; via bottom corner; void growth; Copper; Electromigration; Integrated circuit interconnections; Positron emission tomography; Process control; Resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location
Stanford Sierra, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-8521-5
Type
conf
DOI
10.1109/IIRW.2010.5706499
Filename
5706499
Link To Document