Evaluation on the reliable operation of a Gate-Level Pipelined Self Synchronous system against PVT and aging

The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic blocks. Throughput has been measured at 2.97GHz at 1.2V, with correct operation from 750mV to 1.6V at 25°C. The operation with errors being inserted into the SSFPGA was compared to a conventional synchronous FPGA, which showed the SSFPGA had 4.2 times error free operation. The effect of aging was also measured on the SSFPGA using accelerated cycle between 0°C and 120°C at 2V, which showed the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems..