High efficiency CMOS Class E power amplifier using 0.13 µm technology

Author

Murad, S.A.Z. ; Ahamd, M.F. ; Shahimin, M. Mohamad ; Ismail, R.C. ; Cheng, K.L. ; Sapawi, R.

Author_Institution

Sch. of Microelectron. Eng., Univ. Malaysia Perlis, Arau, Malaysia

fYear

2012

fDate

23-26 Sept. 2012

Firstpage

85

Lastpage

88

Abstract

This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-μm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with on-chip input and output impedance matching. The simulation results indicate that the PA delivers 11.9 dBm output power and 53% power added efficiency (PAE) with 1.3-V power supply into a 50-Ω load. The chip layout is 0.27 mm².

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF power amplifiers; impedance matching; Silterra CMOS technology; cascode topology; device stress problem; efficiency 53 percent; frequency 2.4 GHz; high efficiency CMOS class E power amplifier; impedance matching; power added efficiency; resistance 50 ohm; size 0.13 mum; voltage 1.3 V; wireless applications; CMOS integrated circuits; CMOS technology; Impedance matching; Power amplifiers; Power generation; Topology; Wireless communication; Class E; Silterra; output power; power added efficiency; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Technology and Applications (ISWTA), 2012 IEEE Symposium on

Conference_Location

Bandung

ISSN

2324-7843

Print_ISBN

978-1-4673-2209-6

Type

conf

DOI

10.1109/ISWTA.2012.6373883

Filename

6373883