DocumentCode
2412099
Title
TDDB chip reliability in copper interconnects
Author
Bashir, Muhammad ; Kim, Dae Hyun ; Lim, Sung Kyu ; Milor, Linda
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2010
fDate
17-21 Oct. 2010
Firstpage
121
Lastpage
124
Abstract
Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.
Keywords
circuit optimisation; electric breakdown; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; integrated circuit reliability; Cu; TDDB chip reliability; backend reliability; chip lifetime; circuit reliability; copper interconnects; layout optimizations; layout statistics; time dependent dielectric breakdown; Dielectric breakdown; Dielectrics; Integrated circuit reliability; Layout; Metals; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location
Stanford Sierra, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-8521-5
Type
conf
DOI
10.1109/IIRW.2010.5706503
Filename
5706503
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