DocumentCode
2412216
Title
New DRAM HCI qualification method emphasizing on repeated memory access
Author
Chia, Pierre Chor-Fung ; Wen, Shi-Jie ; Baeg, Sang H.
fYear
2010
fDate
17-21 Oct. 2010
Firstpage
142
Lastpage
144
Abstract
This paper proposes a new accelerated HCI reliability stress method specifically targeting DRAM components. The merit of this stress method is to provide the worst case design requirement of the data word access rate.
Keywords
DRAM chips; hot carriers; integrated circuit design; integrated circuit reliability; life testing; DRAM HCI qualification method; DRAM components; accelerated HCI reliability stress method; data word access rate; repeated memory access; worst case design requirement; Degradation; Human computer interaction; Random access memory; Reliability; Stress; Timing; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location
Stanford Sierra, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-8521-5
Type
conf
DOI
10.1109/IIRW.2010.5706509
Filename
5706509
Link To Document