Platform-based testbench generation

Author

Henftling, R. ; Zinn, A. ; Bauer, M. ; Ecker, W. ; Zambaldi, M.

Author_Institution

Corporate Logic, Infineon Technol. AG, Munich, Germany

fYear

2003

fDate

2003

Firstpage

1038

Lastpage

1043

Abstract

This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.

Keywords

automatic test software; encoding; field programmable gate arrays; hardware description languages; integrated circuit testing; synchronisation; FPGAs; configurable testbench architecture; emulators; generic controllers; instruction encoding; microprogram generation; platform-based test bench generation; protocol-specific stimuli generators reuse; synthesizable testbench architecture; system verification; Acceleration; Control system synthesis; Design automation; Field programmable gate arrays; Hardware; Logic design; Protocols; Test pattern generators; Testing; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253741

Filename

1253741